1. Field of the Invention
This invention relates to a method and system for computing the Hamming distance between two vectors in an N-dimensional space with binary components and to a method and system for comparing the Hamming distance with a preselected value and a method of changing the pre-selected value, if found to be too small, with a single digital command.
2. Brief Description of the Prior Art
Architecture for a complete pattern classifier has been developed by Nestor Learning Systems and is set forth in "Neural Network Algorithms and Implementations" by Dean R. Collins et al., Texas Instruments Incorporated, "Pattern Class Degeneracy In An Unrestricted Storage Density Memory" by Christopher L. Scofield et al., Nestor, Inc., American Institute of Physics, 1988, pages 674 to 682, "Learning System Architectures Composed of Multiple Learning Modules" by Douglas L. Reilly et al., Nestor Inc., pages II-495 to II-503 and "Learning Systems Based on Multiple Neural Networks", copies of which are attached hereto and the contents of which are incorporated herein by reference. However, though the mathematics for the Nestor architecture has been developed, there is no known prior art which implements this architecture in an integrated circuit. It is apparent that a full digital implementation of the mathematics embodying the Nestor architecture has the disadvantage that the Hamming distance must be computed with some type of digital adder, such as a counter, and many N clock cycles are required to compute the required sum, where N is the pattern space dimension which could be 100 or more. The requirement of the many N clock cycles results in the necessity of a relatively high clock rate of N times the pattern rate. Also, the number of components required is relatively large, therefore resulting in a relatively large chip and the concomitant relatively high power consumption. It is therefore apparent that an integrated circuit embodiment of the Nestor architecture which operates with relatively low power consumption, yet operates at sufficiently high speed to perform the classification logic, is highly desirable.